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Hardware description languages
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#	Item
201	WILLEMS LAYOUT[removed]:43 AM Add to Reading List Source URL: www.synopsys.com Language: English Logic design Hardware description languages Hardware verification languages Post-silicon validation Prototype FPGA prototype Field-programmable gate array System on a chip Transaction-level modeling Electronic engineering Electronic design automation Electronic design
202	White Paper Benefits of Using ESP in Memory Designs May 2010 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-04 07:15:42 Hardware description languages Logic design Logic simulation VHDL Standard cell Functional verification SPICE Verilog Simulation Electronic engineering Electronic design automation Digital electronics
203	Datasheet VCS Xprop Increasing the Efficiency of X-related Simulation and Debug Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:23 Hardware verification languages Digital electronics Verilog VHDL Logic simulation Register-transfer level SystemC Logic synthesis Synopsys Electronic engineering Electronic design automation Hardware description languages
204	Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:22 Hardware description languages SystemVerilog OpenVera E Functional verification Synopsys Open Verification Methodology Verilog Logic simulation Electronic engineering Electronic design automation Hardware verification languages
205	Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:30 Formal methods Physical design SystemVerilog Synopsys Formal verification Verilog Formal equivalence checking Signoff Electronic engineering Electronic design automation Hardware description languages
206	Datasheet Verdi3 Automated Debug System Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-01-20 19:15:21 Hardware verification languages Hardware description languages Logic design SystemVerilog Debugging E Logic simulation VHDL Timing closure Electronic engineering Electronic design automation Digital electronics
207	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
208	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:31:02 High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
209	The Best of Both Worlds: Productivity & Performance `` Best Quality of Results for Timing Performance and Area/Cost Reduction Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-12 14:15:25 Fabless semiconductor companies Digital electronics Electronic design Logic synthesis Field-programmable gate array VHDL Synopsys Application-specific integrated circuit High-level synthesis Electronic engineering Electronic design automation Hardware description languages
210	-17 March 9, 2002 An Efficient C++ Framework for Cycle-Based Simulation J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2002-08-16 14:55:21 Logic design SystemC Logic simulation Simulation VHDL Field-programmable gate array Verilog Integrated circuit design Parallel computing Electronic engineering Digital electronics Hardware description languages

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